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Physical Design Engineer

OpenAI

Physical Design Engineer is a still-open role at OpenAI on Jobrow. Location: On-site · San Francisco · California · United States. Listed pay: $266k–$445k. Sourced from the company's public Ashby board. First seen 2 months ago; last confirmed 9 days ago. Apply on the employer ATS — Jobrow is not the employer.

Pay
$266k–$445k
Workplace
On-site
Location
San Francisco · California · United States
First seen
2 months ago
Last seen
9 days ago
Board
Ashby
Apply

About this role

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads.

  • Function: Engineering
  • Seniority: mid
  • python

Location & pay

On-site · San Francisco · California · United States Listed pay on Jobrow: $266k–$445k.

Source

Jobrow reads the public Ashby board for OpenAI. First seen 2 months ago; last seen 9 days ago. We are not the employer — apply only on the company ATS.

Posting

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators. You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality. In this role, you will: - Develop, build and own tools, flows and methodologies for physical implementation - Own physical implementation of floorplan blocks from floorplanning to final signoff - Collaborate with RTL designers to drive optimal block implementation solutions - Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners Qualifications: - BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development - Demonstrated success in taping out complex silicon designs - Hands-on experience with block physical implementation and PPA convergence - Strong coding experience with python, bazel, TCL - Strong experience building physical design tools, flows and methodologies - Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure. - Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation Bonus: - Experience with AI or HPC-focused chips - Experience with optimizing PPA for high performance compute cores - Hands-on experience with top-level design methodologies To comply with U.S. export control laws and regulations, candidates for this role

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