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RTL Design Engineer – Interconnect & Network Datapath

OpenAI

RTL Design Engineer – Interconnect & Network Datapath is a still-open role at OpenAI on Jobrow. Location: Hybrid · San Francisco · California · United States. Listed pay: $225k–$445k. Sourced from the company's public Ashby board. First seen 2 months ago; last confirmed 9 days ago. Apply on the employer ATS — Jobrow is not the employer.

Pay
$225k–$445k
Workplace
Hybrid
Location
San Francisco · California · United States
First seen
2 months ago
Last seen
9 days ago
Board
Ashby
Apply

About this role

ABOUT THE TEAM OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads.

  • Function: Engineering
  • Seniority: mid

Location & pay

Hybrid · San Francisco · California · United States Listed pay on Jobrow: $225k–$445k.

Source

Jobrow reads the public Ashby board for OpenAI. First seen 2 months ago; last seen 9 days ago. We are not the employer — apply only on the company ATS.

Posting

ABOUT THE TEAM OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. ABOUT THE ROLE We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. IN THIS ROLE, YOU WILL: - Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. - Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring. - Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems. - Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work. - Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize la

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