Research Engineer, AI for Chip Design
OpenAI
Research Engineer, AI for Chip Design is a still-open role at OpenAI on Jobrow. Location: Hybrid · San Francisco · California · United States. Listed pay: $380k–$500k. Sourced from the company's public Ashby board. First seen 2 months ago; last confirmed 9 days ago. Apply on the employer ATS — Jobrow is not the employer.
- Pay
- $380k–$500k
- Workplace
- Hybrid
- Location
- San Francisco · California · United States
- First seen
- 2 months ago
- Last seen
- 9 days ago
- Board
- Ashby
About this role
ABOUT THE TEAM OpenAI develops models that can reason through complex problems and hardware designed for the demands of advanced AI.
- Function: Machine learning
- Seniority: mid
Location & pay
Hybrid · San Francisco · California · United States Listed pay on Jobrow: $380k–$500k.
Source
Jobrow reads the public Ashby board for OpenAI. First seen 2 months ago; last seen 9 days ago. We are not the employer — apply only on the company ATS.
Posting
ABOUT THE TEAM OpenAI develops models that can reason through complex problems and hardware designed for the demands of advanced AI. AI for Chips connects these efforts: applying increasingly capable AI systems to the work of semiconductor engineering. Our goal is to help engineers develop better chips and shorten design cycles. This work brings research, model training, and hardware expertise together to build tools that engineers can use on real designs, with correctness and measurable performance at the center. ABOUT THE ROLE We’re hiring a Research Engineer to help OpenAI models solve chip-design problems through reinforcement learning, tool use, and evaluation. You’ll own experiments from the initial idea through implementation and analysis. That means building environments and evaluations, running training, investigating failures, and using the results to decide what to try next. You’ll also build the software needed to make those experiments reliable and reproducible. We value strong coding fundamentals, careful experimental judgment, and the ability to make progress independently. Prior chip-design experience is helpful, but you can learn the domain alongside the team’s hardware specialists. IN THIS ROLE, YOU WILL: - Build RL environments and evaluations for tasks such as RTL generation, design verification, and physical design optimization. - Develop and test approaches that help models use chip-design tools and improve power, performance, and area while preserving correctness. - Design experiments, establish baselines, and measure whether improvements hold up on new tasks and designs. - Investigate failures across model behavior, rewards, evaluation tools, and experiment infrastructure. - Improve iteration speed through better tooling, faster evaluations, and proxy rewards that reflect the outcomes we care about. - Turn successful experiments into reusable research code and training workflows, working closely with researchers and engineers. YOU MIGHT THRIVE IN THIS ROLE IF YOU: - Have strong programming and debugging skills and a track record of turning technical ideas into working software. - Experience with reinforcement learning, model evaluations, post-training, or other applied ML research. - Experience building tool-using agents, reward functions, or automated evaluation systems. - Can form clear hypotheses, design useful experiments, and distinguish meaningful results from noise or evaluation errors. -
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