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ASIC Firmware Engineer, Modeling

OpenAI

ASIC Firmware Engineer, Modeling is a still-open role at OpenAI on Jobrow. Location: On-site · San Francisco · California · United States. Listed pay: $226k–$445k. Sourced from the company's public Ashby board. First seen 2 months ago; last confirmed 9 days ago. Apply on the employer ATS — Jobrow is not the employer.

Pay
$226k–$445k
Workplace
On-site
Location
San Francisco · California · United States
First seen
2 months ago
Last seen
9 days ago
Board
Ashby
Apply

About this role

ABOUT THE TEAM OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads.

  • Function: Engineering
  • Seniority: mid
  • rust

Location & pay

On-site · San Francisco · California · United States Listed pay on Jobrow: $226k–$445k.

Source

Jobrow reads the public Ashby board for OpenAI. First seen 2 months ago; last seen 9 days ago. We are not the employer — apply only on the company ATS.

Posting

ABOUT THE TEAM OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. ABOUT THE ROLE We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues. RESPONSIBILITIES - Design and implement drivers for hardware peripherals, including those related to AI chips. - Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model - Design and implement low-latency and high throughput embedded SW to manage HW resources. - Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware. - Collaborate with vendors to integrate their technologies within our systems. - Bring up and debug firmware/driver on new platforms. - Come up with processes and debug issues raised in the field. - Set up monitoring, integration testing and diagnostics tools. QUALIFICATIONS - 5+ years of experience working in embedded SW space. - Ability to thrive in ambiguity and learn new technologies. - Strong programming skills in C/C++ and/or Rust. - Experience developing high throughput, low latency and multi-threaded code. - Experience working with real time operating systems (RTOS). - Experience developing hardware drivers and working with hardware - Experience with HW/SW co-design - Knowledge of common embedded protocols, e.g. UART, I2C, SPI, etc. - Knowledge of microprocessor and common ARM architectures (e.g. AMBA) is a plus. - Knowledge of PCIe, ethernet and other high BW communication protocols is a plus. - Experience with GPUs or other compute hardware is a plus. - Experience deploying large compute clusters is a plus. To comply with U.S. export control laws and regulations, candidates for this role may need to meet cer

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